This invention generally relates to semiconductor devices and processes and more specifically to ESD protection in CMOS integrated circuits.
As integrated circuits (ICs) become more complex and more dense, the nominal supply voltage drops. Whereas, once nominal supply voltages were in the 5V range and then the 3.3V range, state of the art ICs today have a nominal supply voltage of approximately 2.5 V. However, these ICs must operate in systems designed for older ICs having a 3.3V nominal supply voltage. Thus, today""s ICs are expected to be able to sustain 3.3 V at the input/output (I/O) pins without excessive leakage or any permanent damage occurring. However, since a gate oxide on the order of 60 xc3x85 is used in the newer ICs, there is a possibility of reliability problems related to gate oxide wear-out based on time dependent dielectric breakdown analysis. In addition, the ICs are expected to be power-up sequence independent. That is, when the supply voltage is at 0 V, the IC needs to be able to tolerate 3.6 volts at the I/O pins without permanent damage or excessive oxide stressing.
These requirements place major restrictions on the electrostatic discharge (ESD) protection circuit design. Gate oxides cannot be connected directly between the at the I/O pads and ground. Thus, typical ESD protection circuits such as the gate-coupled nMOS transistor, low voltage triggered SCRs (silicon-controlled rectifiers) and gate-coupled SCRs cannot be used as they have been in the past. One prior art technique that avoids connecting a gate oxide directly between the internal circuitry at the I/O pins and ground in a modified lateral SCR (MLSCR), shown in FIG. 1. The MLSCR 12 is connected between the I/O pin 14 and ground GND. Unfortunately, the trigger voltage of the MLSCR (about 20V) is higher than the breakdown of a gated-diode junction (typically between 8V and 10V) or a gate oxide (typically about 12V-15V). Hence, a series resistor R is required to enable the voltage at the anode of the MLSCR 12 to reach the SCR trigger level before the internal circuitry 16 is damaged.
Another ESD protection circuit that avoids connecting a gate-oxide directly between the internal circuitry at the I/O pins and ground is a dual-diode circuit, shown in FIG. 2. A first diode 20 is connected between the I/O pin 14 and the supply voltage, Vcc and a second diode 22 is connected between I/O pin 14 and ground, GND. However, this circuit has limitations in submicron devices. The voltage-clamping properties of a reversed biased n+/p diode is one limitation. The on-resistance of a reversed-biased diode in avalanche breakdown is greater than 25 ohms. This limits the capability of high current clamping. Accordingly, there is a need for an improved ESD protection circuit that avoids connecting a gate oxide between internal circuitry and ground.
An ESD protection circuit and method for integrated circuits is described herein. A lateral npn transistor is connected between an I/O pad and ground. A substrate biasing circuit is provided that causes current to be conducted through the substrate resistance during an ESD event. This, in turn, raises the voltage across the substrate resistance and forward-biases the emitter-base junction of the lateral npn thus triggering the lateral npn. The lateral npn is the primary protection device for dissipating ESD current.
An advantage of the invention is providing improved ESD protection for multi-voltage applications in submicron, thin oxide CMOS processes.
A further advantage of the invention is providing improved ESD protection for multi-voltage applications that is independent of the power-up sequence in submicron, thin oxide CMOS processes.
A further advantage of the invention is providing improved ESD protection requiring less area in submicron, thin oxide CMOS processes.
These and other advantages will be apparent to those skilled in the art having reference to the specification in conjunction with the drawings.